On Simulating Parallel Algorithms with VHDL

Hardware Description Languages (HDL) like VHDL are widely used to design and simulate with programmable logic devices. Simulation of very large scale integrated digital systems (VLSI) is of great importance as it assures system correctness and maximizes system performance ([4], [5], [9]). The utilization of parallel simulation introduces the problem of how to partition the logic gates and system behaviors of the circuit among the available processors in order to obtain maximum speedup. This paper presents how a series of sequential statements like VHDL processes and signals can be used to simulate parallel message broadcasts. Processes and signals are the most important VHDL parts for simulation.